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ON Semiconductort
Quad Analog Switch/ Multiplexer/Demultiplexer
MC74VHC4066
High-Performance Silicon-Gate CMOS
The MC74VHC4066 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low O F F -c h a n n e l leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The VHC4066 is identical in pinout to the metal-gate CMOS MC14066 and the high-speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage-level translators, see the VHC4316. * Fast Switching and Propagation Speeds * High ON/OFF Output Voltage Ratio * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 Volts * Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts * Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 * Low Noise * Chip Complexity: 44 FETs or 11 Equivalent Gates
D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03
DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01 ORDERING INFORMATION MC74VHCXXXXD MC74VHCXXXXDT SOIC TSSOP
PIN ASSIGNMENT
XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC
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These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
FUNCTION TABLE
On/Off Control Input L H State of Analog Switch Off On
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 5
1
Publication Order Number: MC74VHC4066/D
XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL
1 13 4 5 8 6 11 12
2
YA
3
YB ANALOG OUTPUTS/INPUTS
9
YC
10
YD
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND
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Symbol VCC VIS Vin I PD Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) DC Current Into or Out of Any Pin Power Dissipation in Still Air, Storage Temperature - 0.5 to + 14.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 25 500 450 mA SOIC Package TSSOP Package mW _C _C Tstg - 65 to + 150 TL Lead Temperature, 1 mm from Case for 10 Seconds 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
Figure 1. Logic Diagram MAXIMUM RATINGS*
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
RECOMMENDED OPERATING CONDITIONS
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Symbol VCC VIS Vin TA Parameter Min 2.0 Max VCC VCC 1.2 Unit V V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch 12.0 GND GND -- - 55 VIO* tr, tf Operating Temperature, All Package Types + 125 _C Input Rise and Fall Time, ON/OFF Control ns Inputs (Figure 14) VCC = 2.0 V 0 1000 VCC = 3.0 V 0 600 VCC = 4.5 V 0 500 VCC = 9.0 V 0 400 0 250 VCC = 12.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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At supply voltage (VCC) approaching 3 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals.
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Symbol
Symbol
Ron
Ron
VIH
ICC
VIL
Ion
Ioff
Iin
Maximum On-Channel Leakage Current, Any One Channel
Maximum Off-Channel Leakage Current, Any One Channel
Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package
Maximum "ON" Resistance
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current ON/OFF Control Inputs
Maximum Low-Level Voltage ON/OFF Control Inputs
Minimum High-Level Voltage ON/OFF Control Inputs
Parameter
Parameter
Vin = VIH VIS = VCC or GND (Figure NO TAG)
Vin = VIH VIS = VCC or GND (Endpoints) IS v 2.0 mA (Figures 2 through 7)
Vin = VIH VIS = VCC to GND IS v 2.0 mA (Figures 2 through 7)
Vin = VIL VIO = VCC or GND Switch Off (Figure NO TAG)
Vin = VIH VIS = 1/2 (VCC - GND) IS v 2.0 mA
Vin = VCC or GND VIO = 0 V
Vin = VCC or GND
Ron = Per Spec
Ron = Per Spec
Test Conditions
Test Conditions
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2.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 6.0 12.0 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 12.0 12.0 2.0 3.0 4.5 9.0 12.0 12.0 VCC V VCC V - 55 to 25_C - 55 to 25_C 0.1 0.5 0.9 1.35 2.7 3.6 1.5 2.1 3.15 6.3 8.4 -- -- 120 70 70 0.1 0.1 -- 20 15 15 -- -- 70 50 30 2 4 Guaranteed Limit Guaranteed Limit v 85_C v 85_C 1.0 0.5 0.9 1.35 2.7 3.6 1.5 2.1 3.15 6.3 8.4 -- -- 160 85 85 0.5 0.5 20 40 -- 25 20 20 -- -- 85 60 60 v 125_C v 125_C 1.0 0.5 0.9 1.35 2.7 3.6 1.5 2.1 3.15 6.3 8.4 -- -- 100 80 80 -- -- 200 100 100 40 160 1.0 1.0 -- 30 25 25 Unit Unit A A A A V V
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ CPD C Power Dissipation Capacitance (Per Switch) (Figure 17)* Maximum Capacitance Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 14 and 15) Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 14 and 15) Maximum Propagation Delay, Analog Input to Analog Output (Figures 18 and 13) Parameter ON/OFF Control Input Control Input = GND Analog I/O Feedthrough 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 VCC V -- -- -- - 55 to 25_C Typical @ 25C, VCC = 5.0 V 35 1.0 10 80 45 20 20 20 80 60 20 20 20 40 30 5 5 5 Guaranteed Limit v 85_C 35 1.0 10 90 50 25 25 25 90 70 25 25 25 50 40 7 7 7 15 v 125_C 100 60 30 30 30 110 80 35 35 35 35 1.0 10 60 50 8 8 8 Unit pF pF ns ns ns
* Used to determine the no-load dynamic power consumption: P D = CPD VCC
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2f
4 + ICC VCC .
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
RON @ 2 V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIII II III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIII I III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Symbol BW Parameter Test Conditions VCC V Limit* 25_C 74HC 150 160 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure NO TAG) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 9.0 12.0 MHz -- Off-Channel Feedthrough Isolation (Figure NO TAG) 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 dB -- Feedthrough Noise, Control to Switch (Figure NO TAG) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF RL = 10 k, CL = 10 pF mVPP -- Crosstalk Between Any Two Switches (Figure 16) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF fin = 1.0 MHz, RL = 50 , CL = 10 pF - 70 - 70 - 70 - 80 - 80 - 80 dB fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Guaranteed limits not tested. Determined by design and verified by qualification. THD Total Harmonic Distortion (Figure 20) % 4.5 9.0 12.0 0.10 0.06 0.04 400 350 300 250 200 150 100 50 0 0.00 0.20 0.40 0.60 0.80 1.00 +25 _C +125_C -55_C 1.20 1.40 1.60 1.80 2.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 2. Typical On Resistance, VCC = 2.0 V
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200 180 160 RON @ 4.5 V 140 120 100 80 60 40 20 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 +25 _C +125_C -55_C
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 3. Typical On Resistance, VCC = 4.5 V
90 80 70 RON @ 6 V 60 50 40 30 20 10 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 +25 _C +125_C -55_C 4.00 4.50 5.00 5.50 6.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 4. Typical On Resistance, VCC = 6.0 V
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90 80 70 RON @ 9V 60 50 40 30 20 10 0 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 +25 _C +125_C -55_C
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 5. Typical On Resistance, VCC = 9.0 V
60 50 RON @ 12 V 40 30 20 10 0 0.00 +25 _C +125_C -55_C 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 6. Typical On Resistance, VCC = 12 V
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PLOTTER
VCC VCC
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
GND VCC A OFF
14
VCC DEVICE UNDER TEST
ANALOG IN
COMMON OUT
7
SELECTED CONTROL INPUT
VIL
GND
Figure 7. On Resistance Test Set-Up
Figure 8. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
VCC VCC VCC A GND ON 14 N/C fin 0.1F ON 14
VOS
CL*
dB METER
7
SELECTED CONTROL INPUT
VIH
7
SELECTED CONTROL INPUT
VCC
*Includes all probe and jig capacitance.
Figure 9. Maximum On Channel Leakage Current, Test Set-Up
Figure 10. Maximum On-Channel Bandwidth Test Set-Up
VIS fin 0.1F RL SELECTED CONTROL INPUT 7 OFF
VCC 14
VOS
VCC/2 14 CL* dB METER RL OFF/ON
VCC
VCC/2
RL IS
VOS CL*
VCC GND *Includes all probe and jig capacitance.
Vin 1 MHz tr = tf = 6 ns CONTROL
7
SELECTED CONTROL INPUT
*Includes all probe and jig capacitance.
Figure 11. Off-Channel Feedthrough Isolation, Test Set-Up
Figure 12. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up
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VCC 14 VCC ANALOG IN tPLH 50% 50% GND tPHL 7 SELECTED CONTROL INPUT VCC ANALOG IN ON ANALOG OUT CL* TEST POINT
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 18. Propagation Delays, Analog In to Analog Out
Figure 13. Propagation Delay Test Set-Up
POSITION 1 WHEN TESTING tPHZ AND tPZH tr CONTROL 90% 50% 10% tPZL 50% ANALOG OUT 50% tPZH tPHZ 90% VOH HIGH IMPEDANCE tPLZ tf VCC GND HIGH IMPEDANCE 10% VOL VCC 1 2 ON/OFF CL* SELECTED CONTROL INPUT 7 *Includes all probe and jig capacitance. 1 2 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 k TEST POINT
Figure 14. Propagation Delay, ON/OFF Control to Analog Out
Figure 15. Propagation Delay Test Set-Up
VIS VCC fin 0.1 F OFF VCC OR GND RL SELECTED CONTROL INPUT 7 VCC/2 *Includes all probe and jig capacitance. RL CL* RL CL* N/C OFF/ON RL ON 14 VOS 14 N/C A VCC
VCC/2
VCC/2 7
SELECTED CONTROL INPUT
ON/OFF CONTROL
Figure 16. Crosstalk Between Any Two Switches, Test Set-Up
Figure 17. Power Dissipation Capacitance Test Set-Up
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0 VIS 0.1 F fin ON RL VCC/2 7 SELECTED CONTROL INPUT VCC CL* VCC -10 VOS TO DISTORTION METER -20 -30 dBm -40 -50 -60 -70 -80 -90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY
*Includes all probe and jig capacitance.
Figure 20. Total Harmonic Distortion, Test Set-Up
Figure 19. Plot, Harmonic Distortion the example below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 21, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 22. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (high current surge protectors). Mosorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism.
APPLICATION INFORMATION
The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages V CC and GND. The positive peak analog voltage should not exceed V CC . Similarly, the negative peak analog voltage should not go below GND. In
VCC = 12 V + 12 V 0V SELECTED CONTROL INPUT 7 ANALOG I/O 14 ON ANALOG O/I + 12 V 0V Dx VCC Dx
VCC 16 ON
VCC Dx
Dx SELECTED CONTROL INPUT 7
OTHER CONTROL INPUTS (VCC OR GND)
OTHER CONTROL INPUTS (VCC OR GND)
Figure 21. 12 V Application
Figure 22. Transient Suppressor Application
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+5 V
+5 V
ANALOG SIGNALS R* R* R* R* 5 6 14 15 R* = 2 TO 10 k
14
ANALOG SIGNALS
ANALOG SIGNALS VHCT BUFFER 5 6 14 15
14
ANALOG SIGNALS
LSTTL/ NMOS
VHC4066
LSTTL/ NMOS
VHC4066
CONTROL INPUTS 7
CONTROL INPUTS 7
a. Using Pull-Up Resistors
b. Using HCT Buffer
Figure 23. LSTTL/NMOS to HCMOS Interface
VDD = 5 V
VCC = 5 TO 12 V
13 3 5 7 9 11 14
1
16
ANALOG SIGNALS
14 VHC4066
ANALOG SIGNALS
MC14504
2 4 6 10
5 6 14 15 CONTROL INPUTS 7
8
Figure 24. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V (Also see VHC4316)
CHANNEL 4
1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES INPUT 1 OF 4 SWITCHES - 1 OF 4 SWITCHES + 0.01 F LF356 OR EQUIVALENT
CHANNEL 3
CHANNEL 2
OUTPUT
CHANNEL 1
1
2 34 CONTROL INPUTS
Figure 25. 4-Input Multiplexer http://onsemi.com
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Figure 26. Sample/Hold Amplifier
OUTLINE DIMENSIONS D SUFFIX SOIC-14 CASE 751A-03 ISSUE F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G
C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
DT SUFFIX TSSOP CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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C E CC CEC C EEC CC
A -V-
K1
SECTION N-N -W-
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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